For 5 nm and beyond nodes, with the continually increasing demand for smaller circuit structures and faster device performance, the need for increased current density has resulted in the development of vertical field effect transistors (VFETs). However, realization of VFETs with replacement metal gate (RMG) structures is complex, due to the placement of the gate structure below the source and drain structure, greatly increasing the complexity of these structures and limiting the thermal budgets of the resultant devices.
Therefore, it is desirable to develop methods of fabricating VFET structures which enable the integration of replacement gate structures at high density.